The present invention relates to techniques for recycling address signals for a memory circuit, and more particularly, to techniques for storing an address signal for a memory circuit during a stall cycle for subsequent use.
In most systems on a chip (SOC) designs, a sequential machine such as a microprocessor or a microcontroller plays a central role in distributing signals through the SOC. A sequential machine requires a sharable memory or two separated memories to store and to load instructions and data.
The majority of a computer system's operations are spent performing memory load and store functions. For this reason, efforts have been made to reduce both memory access time within a clock cycle and the latency of memory data flow to improve the overall performance of computer systems.
On such solution involves cache memory architecture. In cache memory architecture, embedded memory and control logic units are placed together on the same silicon chip to shorten the memory access time between separated stand-alone chips. Cache memory architecture also reduces the latency of memory clock cycles. However, some types of cache memories do not offer all of these benefits.
Sometimes the system control logic uses a virtual memory addressing scheme. In other instances, the physical size of the cache memory does not match the size of a logical address. In these situations, the cache memory has to collaborate with extra circuitry and other small memories to form a memory management unit (MMU).
The control logic of the MMU schedules different latency times of clock cycles for various cache operations depending on individual needs. Sometimes the cache memory has to spend one or more additional clock cycles to finish a memory store or load data. The extra time required for the additional clock cycles eliminates the time savings provided by using cache memory in the first place.
Many types of SOC systems include programmable logic devices (PLDs). As the memory demands of SOC systems grow, the memory of PLDs also needs to be enhanced to meet the increased demands. As a result, an increased need is developing to improve latency access times for memories in PLDs and on SOC systems.
A typical dual-port static read access memory (SRAM) block on a PLD includes an SRAM core, two programmable input/output interfaces to programmable interconnect lines, two sets of data registers, two sets of control registers, and two sets of address registers. The address registers are controlled by a clock signal for signal synchronization. The SRAM core includes a memory array and address decoder circuitry.
Address signals are transmitted from through the programmable interconnect to an SRAM block through configurable multiplexers and driver circuits. The address signals are stored temporarily in the address registers. The address registers store a new address signal at each rising edge of the clock signal. The address decoder circuitry decodes each address signal and uses the decoded address signals to select word lines in the SRAM memory array to access data stored at the decoded addresses.
When an SRAM block in a PLD is used by an MMU as a cache memory, data is read from the cache memory in data blocks. When an entire block of data has been read from the cache memory, a new block of data is stored in the cache. A stall state is initiated when the data stored within the SRAM cache memory is refreshed with a new set of data. During the stall state, the read port address might be changed and irrelevant to the cache memory for supporting different block in the system. Because the address signals cannot be used to access data in the memory cache during the stall state, address signals that were transmitted to the memory cache immediately before the start of the stall state are lost.
When the stall state ends, the memory block has to reload address signals lost prior to the stall state. It takes additional time and clock cycles to reload these address signal, significantly slowing down overall memory access time. Therefore, there is a need to provide techniques for recycling address signals in memory circuits during a stall state that minimizes read access latency delays.